A DRAM generally includes a two-dimensional array of rows and columns of memory cells integrated in a semiconductive chip. A popularly used memory cell with n-channel metal-oxide-silicon (MOS) DRAMs is the "switched capacitor" memory cell which has a n-channel MOS transistor (also denoted as a pass transistor) and a capacitor (also denoted as a storage device). One output terminal of the transistor is coupled to a first terminal (storage plate) of the capacitor and the second terminal (reference plate) of the capacitor is typically coupled to a fixed voltage source. The gates of all of the transistors of a common row of memory cells are coupled to a common word line and the second output terminals of the pass transistors of a column of memory cells are all coupled to a common separate bit line. In a n-channel MOS transistor positive current is defined as flowing along the channel from the drain to the source output terminals. During operation of the switched capacitor memory cell current reverses through the transistor and thus the drain and source reverse. For the sake of discussion herein the first output terminal of the pass transistor shall be denoted as the source and the second output terminal shall be denoted as the drain.
In its early form, both the channel of the pass transistor and the storage surface of the capacitor extended largely horizontally along the active surface area of the chip. This latter characteristic was found to limit the density with which the memory cells could be packed in a single chip because, to achieve the desired amount of capacitance necessary for reliability, it was important to use considerable active surface area for the capacitor.
To meet this problem, it has become the practice to employ in high density DRAMs a memory cell that uses a capacitor whose storage surface extends essentially perpendicular to the active surface area, typically in a trough (trench) that extends vertically in the chip so that the capacitance can be increased as needed, simply by extending the depth of the trench with little effect on the chip surface area consumed by the capacitor.
In U.S. Pat. No. 5,376,575, which issued on Dec. 27, 1994, there is proposed a DRAM that reverses this approach and employs a storage capacitor at the active surface of the chip whose storage surface extends parallel to the active surface and a buried pass transistor that underlies the storage capacitor and whose channel extends vertically in a trench that extends vertically from the active surface. This design permits the bit line that normally extends over the active surface of the chip to be buried in the interior of the chip, thereby saving the area of the active surface of the chip formerly occupied by the bit line. Additionally, the vertical orientation of the transistor permits the length of the channel of the transistor to be increased, as needed, to avoid undesirable short-channel effects that generally limit how much the channel length can be effectively shortened. However, the burial of the bit lines can complicate the fabrication process, particularly in dense arrays where each bit line needs to serve all the cells in a column. Presently there is known no report in the literature of a memory cell of this kind, but its manufacture would appear to be difficult for use in state of the art DRAMs.
Another problem that arises with increasing the density of memory cells in an array is the increasing difficulty in achieving consistently the alignment required of the various processes involved in the commercial manufacture of such arrays.
It is desirable to have a switched capacitor memory cell that requires relatively little semiconductor surface area, has adequate capacitance, and can be fabricated relatively easily.